SN74LVC1G175 Single D-Type Flip-Flop with Asynchronous Clear

01 · Device purpose

Product Overview and Selection Scope

SN74LVC1G175 contains one positive-edge-triggered D-type flip-flop with an active-low asynchronous clear input.

Wide supply range: 1.65 V to 5.5 V operation.
Edge-triggered storage: with CLR HIGH, Q captures D on the rising edge of CLK.
Asynchronous clear: CLR LOW forces Q LOW regardless of CLK or D.
5.5 V input acceptance: data and control inputs are specified from 0 V to 5.5 V.
Output drive: ±24 mA at V_CC = 3.0 V under the specified DC tests.
Partial power-down: I_off supports live insertion, back-drive protection and powered-down interfaces.

Selection boundary: This device stores one bit. It is not a latch, clock divider, multibit register, synchronizer qualification or metastability guarantee. Verify setup, hold, pulse-width and propagation limits for the real clock and data paths.

02 · Logic and pins

Positive-Edge Capture, Asynchronous Clear and Pin Assignment

With CLR HIGH, the rising clock edge transfers D to Q. CLR LOW has priority and forces Q LOW without waiting for a clock edge.

SN74LVC1G175 positive-logic diagram — Positive-logic diagram from the supplied specification.

SN74LVC1G175 top-view pin configuration and function table — Common SOT23-6 / SC70-6 top view and functional behavior.

Pin	Name	Type	Function	Engineering note
1	CLK	Input	Clock input	Q captures D on the rising edge when CLR is HIGH.
2	GND	Power	Ground	Use a short local return path.
3	D	Input	Data input	Meet setup and hold requirements around CLK ↑.
4	Q	Output	Stored data output	Check output load and receiver thresholds.
5	VCC	Power	Supply	Place local bypass capacitance close to pins 5 and 2.
6	CLR	Input	Active-low asynchronous clear	LOW forces Q LOW regardless of CLK and D.

03 · Orderable options

Ordering Codes and Package Selection

Ordering number	Temperature range	Package	Top marking	MSL	Packing
SN74LVC1G175DCKR	-40 °C to +125 °C	SC70-6 / SOT363 equivalent	D65	MSL 3	Tape and reel, 3,000 units
SN74LVC1G175DBVR	-40 °C to +125 °C	SOT23-6	C755	MSL 3	Tape and reel, 3,000 units

Additional lot, date, vendor, logo or environmental markings may appear. Confirm the complete ordering code and package drawing during receiving inspection.

04 · Design envelope

Recommended Operating Conditions and Absolute Limits

Parameter	Condition	Minimum	Maximum	Unit
Supply voltage, VCC	Operating	1.65	5.5	V
Input voltage, VI	Operating	0	5.5	V
Output voltage, VO	Operating	0	VCC	V
Input transition, Δt/Δv	1.8 V / 2.5 V supplies	-	20	ns/V
Input transition, Δt/Δv	3.3 V / 5 V supplies	-	10	ns/V
Ambient temperature, TA	Operating	-40	125	°C

Input logic thresholds

VCC range	VIH minimum	VIL maximum	Unit
1.65 V to 1.95 V	0.75 × VCC	0.25 × VCC	V
2.3 V to 2.7 V	1.7	0.7	V
3.0 V to 3.6 V	2.0	0.8	V
4.5 V to 5.5 V	0.7 × VCC	0.3 × VCC	V

Absolute maximum and handling limits

Parameter	Minimum	Maximum	Unit
Supply voltage, VCC	-0.5	6.5	V
Input voltage, VI	-0.5	6.5	V
Output voltage, high-impedance or power-off	-0.5	6.5	V
Output voltage, HIGH or LOW state	-0.5	VCC + 0.5	V
Continuous output current	±50		mA
Continuous VCC or GND current	±100		mA
Junction / storage temperature	-65	150	°C

Thermal impedanceθJA = 230 °C/W for SOT23-6 and 265 °C/W for SC70-6.

ESD ratingsHBM ±2000 V, CDM ±1000 V and MM ±200 V.

HandlingUse an ESD-protected area and validate the actual PCB thermal environment.

05 · Static performance

Output Levels, Leakage and Supply Current

Parameter	Test condition	VCC	Limit or typical value	Unit
VOH	IOH = -100 µA	1.65 V to 5.5 V	Minimum VCC - 0.1 V	V
VOH	IOH = -4 / -8 / -16 / -24 / -32 mA	1.65 / 2.3 / 3.0 / 3.0 / 4.5 V	Minimum 1.2 / 1.9 / 2.4 / 2.3 / 3.8 V	V
VOL	IOL = 100 µA	1.65 V to 5.5 V	Maximum 0.1 V	V
VOL	IOL = 4 / 8 / 16 / 24 / 32 mA	1.65 / 2.3 / 3.0 / 3.0 / 4.5 V	Maximum 0.45 / 0.30 / 0.40 / 0.55 / 0.55 V	V
II	Data or control input at 5.5 V or GND	0 V to 5.5 V	±0.1 µA typical; ±5 µA maximum full range	µA
Ioff	VI or VO = 5.5 V	0 V	±0.1 µA typical; ±10 µA maximum full range	µA
ICC	VI = 5.5 V or GND, IO = 0	1.65 V to 5.5 V	0.1 µA typical; 10 µA maximum full range	µA
ΔICC	One input at VCC - 0.6 V	3 V to 5.5 V	500 µA maximum	µA
Ci	VI = VCC or GND	3.3 V	5.5 pF typical	pF

Input boundary: All unused inputs must be held at VCC or GND. A 5.5 V-tolerant input does not remove setup, hold, pulse-width or input-transition requirements.

06 · Dynamic performance

Timing Requirements and Switching Characteristics

Timing limits depend on supply, temperature and capacitive load. The 30 pF / 50 pF table below uses the full -40 °C to +125 °C propagation limits listed in the supplied specification.

Requirement	1.8 V	2.5 V	3.3 V	5.0 V	Scope / unit
Clock HIGH or LOW pulse width	8	4	3	2	ns min., -40 °C to +85 °C
CLR LOW pulse width	12	5	3.4	2	ns min., -40 °C to +85 °C
Data setup time	10.4	4.6	3.2	2	ns min., -40 °C to +85 °C
CLR inactive setup time	8.4	3.8	2.6	1.8	ns min., -40 °C to +85 °C
Data hold time	0.5	0.5	0.5	0.5	ns min., -40 °C to +85 °C

For -40 °C to +125 °C operation, the PDF lists 3.3 V / 5.0 V minima of 3 / 2 ns for CLK pulse width, 3.4 / 2 ns for CLR LOW pulse width, 3.2 / 2 ns for data setup, 2.6 / 1.8 ns for CLR inactive setup, and 0.5 / 0.5 ns for hold.

Path	1.8 V	2.5 V	3.3 V	5.0 V	Unit / condition
CLK to Q, tpd min / max	2.7 / 28.3	2.2 / 15	1.6 / 11.5	1.5 / 9	ns, CL = 30 pF or 50 pF
CLR to Q, tpd min / max	2.7 / 25	2.2 / 12	1.5 / 9.5	1.3 / 7.5	ns, CL = 30 pF or 50 pF
Cpd typical	12	16	21	24	pF at 10 MHz, +25 °C

Simplified SN74LVC1G175 rising-edge capture and asynchronous-clear behavior — Essential behavior only: CLK ↑ captures D; CLR LOW asynchronously forces Q LOW.

07 · Implementation

Clocking, Shift-Register Use and PCB Guidance

Meet setup and hold: keep D stable around the active CLK edge for the specified intervals.
Meet pulse widths: validate both CLK HIGH/LOW and CLR LOW durations at the actual supply and temperature.
Control CLR release: satisfy the inactive-clear setup time before a rising CLK edge.
Do not leave inputs floating: tie unused D, CLK and CLR inputs to defined logic levels.
Avoid output contention: Q actively drives HIGH and LOW; do not connect competing push-pull outputs.
Bypass locally: place a 0.1 µF capacitor close to VCC and GND; the PDF also notes 0.1 µF and 1 µF may be paralleled for broader noise rejection.

Four SN74LVC1G175 devices connected as a 4-bit serial shift register — PDF example: four devices form a 4-bit serial shift register with a common clock.

System check: Validate clock integrity, skew, setup/hold margin, clear sequencing, output loading, power sequencing and metastability risk in the finished design.

08 · Mechanical

SOT23-6 and SC70-6 Packages, Land Patterns and Packing

The two packages share the same logical pin assignment but have different body dimensions, lead pitch, marking and thermal impedance. Do not share one PCB footprint between them.

SN74LVC1G175 SOT23-6 package outline and land pattern — SOT23-6 outline, dimensional table and recommended land pattern.

SN74LVC1G175 SC70-6 package outline and land pattern — SC70-6 outline, dimensional table and recommended land pattern.

Dimension	SOT23-6	SC70-6	Unit
Overall height A	1.050 to 1.250	0.900 to 1.100	mm
Body length D	2.820 to 3.020	2.000 to 2.200	mm
Body width E	1.500 to 1.700	1.150 to 1.350	mm
Overall lead span E1	2.650 to 2.950	2.150 to 2.450	mm
Lead pitch e	0.950 BSC	0.650 BSC	mm
Outer lead pitch e1	1.800 to 2.000	1.300 BSC	mm
Lead width b	0.300 to 0.500	0.150 to 0.350	mm
Lead length L	0.300 to 0.600	0.260 to 0.460	mm

SN74LVC1G175 SOT23-6 and SC70-6 tape-and-reel dimensions — Both packages use a 7-inch reel, 9.5 mm reel width, 8.0 mm carrier tape, 4.0 mm pitch and Q3 pin-1 quadrant.

09 · Use contexts

Application Guidance and Design Limitations

The supplied specification lists the following application areas. These are use contexts, not end-product approvals or safety certifications.

Enterprise SwitchingStore and pipeline compact board-level control states.

Telecom InfrastructureCapture synchronous status or control data in distributed systems.

ServersRetain one-bit control or sequencing states near local logic.

Medical healthcare and fitness application

Medical, Healthcare and FitnessUse only after system-level safety and regulatory validation.

PC and NotebookCapture clocked board-level state in compact computing hardware.

Motor DrivesLatch digital control states outside the high-power drive path.

Qualification boundary: Validate EMC, ESD protection, clock integrity, functional safety, thermal limits, power sequencing, assembly and environmental performance in the finished product.

10 · Engineering answers

SN74LVC1G175 Engineering FAQs

What function does SN74LVC1G175 implement?

With CLR HIGH, Q captures D on each rising CLK edge. CLR LOW forces Q LOW asynchronously.

Does CLR need a clock edge to clear Q?

No. CLR is asynchronous and active LOW, so Q is forced LOW regardless of CLK and D.

What supply range is recommended?

VCC is specified from 1.65 V to 5.5 V for operation.

Can inputs accept 5.5 V when VCC is lower or off?

The recommended input range is 0 V to 5.5 V, and Ioff is specified for partial power-down. Validate all board-level back-power paths.

What timing must be checked?

Check CLK and CLR pulse widths, D setup and hold times, CLR inactive setup time, maximum clock frequency and both CLK-to-Q and CLR-to-Q propagation delay.

Can several devices form a shift register?

Yes. The PDF shows four devices connected with a common clock as a 4-bit serial shift register.

Which packages are listed?

SN74LVC1G175DBVR is SOT23-6 with C755 marking. SN74LVC1G175DCKR is SC70-6 with D65 marking. Both are MSL 3 and tape-and-reel packed in quantities of 3,000.

Can an input be left open?

No. Every unused input must be held at VCC or GND.

Technical source and design authority

This page summarizes the supplied SN74LVC1G175 Rev A.1 product specification for component evaluation. Confirm the current controlled specification, ordering code, marking, pin assignment, timing, package tolerances and qualification requirements before production release.

Download SN74LVC1G175 Product Specification Contact NYFEA for Product Support