SN74LVC1G04 Single Inverter Gate
NYFEA SN74LVC1G04 is a single CMOS inverter specified for 1.65 V to 5.5 V operation. Its input accepts signals from 0 V to 5.5 V, Ioff supports partial-power-down applications, and the device is offered in green SOT23-5 and SC70-5 packages.
Product scope: The device implements Y = ¬A. A LOW input produces a HIGH output and a HIGH input produces a LOW output. It has a push-pull output and is not a Schmitt-trigger inverter, open-drain driver, tri-state buffer or analog switch.
Use the current controlled PDF for threshold limits, output loading, switching conditions, package tolerances, tape orientation and production-release decisions.
Product Overview and Selection Scope
SN74LVC1G04 integrates one inverting logic stage. The output reproduces the logical complement of input A. The specified operating supply is 1.65 V to 5.5 V, while the recommended input and output voltage ranges extend from 0 V to 5.5 V. Signal-level compatibility, power sequencing and current paths must still be validated at system level.
Signal role
Input A drives one push-pull output Y through an inverting stage. Pin 1 is not connected; there is no output-enable state.
Voltage domain
VCC is 1.65 V to 5.5 V for operation. VIH and VIL limits change with VCC; use the complete threshold table.
Power-down behavior
Ioff is specified with VCC = 0 V and VI or VO = 5.5 V to limit current through the powered-down device path.
Package choice
SOT23-5 and SC70-5 are both listed, each with its own ordering code, top marking, land pattern and thermal impedance.
Selection boundary: The PDF does not specify Schmitt-trigger hysteresis, open-drain operation, tri-state control, analog switching or end-product qualification. Use a Schmitt-trigger device for slow or noisy inputs and another output architecture where wired logic or high impedance is required.
Logic Function, Truth Table and Pin Assignment
The Boolean function is Y = ¬A. A HIGH input drives Y LOW, while a LOW input drives Y HIGH.
| Pin | Name | Type | Function | Engineering note |
|---|---|---|---|---|
| 1 | N.C. | - | Not connected | Do not use as a signal or supply connection. |
| 2 | A | Input | Inverting logic input | Hold at VCC or GND when unused. |
| 3 | GND | Power | Ground | Use a short return to the local bypass capacitor. |
| 4 | Y | Output | Push-pull inverted output | Do not connect to another active output. |
| 5 | VCC | Power | Supply | Place local decoupling near pins 5 and 3. |
Ordering Codes and Package Selection
| Ordering number | Temperature range | Package | Top marking | MSL | Packing |
|---|---|---|---|---|---|
| SN74LVC1G04DCKR | -40 °C to +125 °C | SC70-5 / SOT353 equivalent | CCF | MSL 3 | Tape and reel, 3,000 units |
| SN74LVC1G04DBVR | -40 °C to +125 °C | SOT23-5 | C04F | MSL 3 | Tape and reel, 3,000 units |
Additional lot, date, vendor, logo or environmental markings may appear. Confirm the full order code, package dimensions, marking and reel orientation during receiving inspection.
Recommended Operating Conditions and Absolute Limits
Recommended operating conditions define the functional design range. Absolute maximum ratings are stress limits only and do not establish normal operation or long-term reliability.
| Parameter | Condition | Minimum | Maximum | Unit |
|---|---|---|---|---|
| Supply voltage, VCC | Operating | 1.65 | 5.5 | V |
| Supply voltage, VCC | Data retention only | 1.5 | - | V |
| Input voltage, VI | Operating | 0 | 5.5 | V |
| Output voltage, VO | Operating | 0 | 5.5 | V |
| Input rise/fall, tr or tf | VCC = 1.8 V ±0.15 V or 2.5 V ±0.2 V | - | 20 | ns/V |
| Input rise/fall, tr or tf | VCC = 3.3 V ±0.3 V | - | 10 | ns/V |
| Input rise/fall, tr or tf | VCC = 5 V ±0.5 V | - | 5 | ns/V |
| Ambient temperature, TA | Operating | -40 | 125 | °C |
Absolute maximum and handling limits
| Parameter | Condition | Minimum | Maximum | Unit |
|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 6.5 | V |
| Input voltage | VI | -0.5 | 6.5 | V |
| Output voltage | High-impedance or power-off state | -0.5 | 6.5 | V |
| Output voltage | HIGH or LOW state | -0.5 | VCC + 0.5 | V |
| Input clamp current | VI < 0 V | -50 | mA | |
| Output clamp current | VO < 0 V | -50 | mA | |
| Continuous output current | IO | ±50 | mA | |
| Continuous VCC or GND current | - | ±100 | mA | |
| Junction temperature | TJ | -65 | 150 | °C |
| Storage temperature | Tstg | -65 | 150 | °C |
DC Characteristics and Logic Levels
Unless otherwise noted, full-range limits apply from -40 °C to +125 °C. Typical values are characterized at +25 °C and are not guaranteed production limits.
| VCC range | VIH minimum | VIL maximum | Engineering interpretation |
|---|---|---|---|
| 1.65 V to 1.95 V | 0.65 × VCC | 0.35 × VCC | Thresholds scale with supply. |
| 2.3 V to 2.7 V | 1.7 V | 0.7 V | Use the fixed guaranteed limits. |
| 3.0 V to 3.6 V | 2.0 V | 0.8 V | Use the fixed guaranteed limits. |
| 4.5 V to 5.5 V | 0.70 × VCC | 0.30 × VCC | Thresholds scale with supply. |
Output levels, leakage and supply current
| Parameter | Test condition | VCC | Temperature | Limit or typical value | Unit |
|---|---|---|---|---|---|
| VOH | IOH = -100 µA | 1.65 V to 5.5 V | Full | Minimum VCC - 0.1 V | V |
| VOH | IOH = -4 / -8 / -16 / -24 / -32 mA | 1.65 / 2.3 / 3.0 / 3.0 / 4.5 V | Full | Minimum 1.2 / 1.9 / 2.4 / 2.3 / 3.8 V | V |
| VOL | IOL = 100 µA | 1.65 V to 5.5 V | Full | Maximum 0.1 V | V |
| VOL | IOL = 4 / 8 / 16 / 24 / 32 mA | 1.65 / 2.3 / 3.0 / 3.0 / 4.5 V | Full | Maximum 0.45 / 0.30 / 0.40 / 0.55 / 0.55 V | V |
| II | A at 5.5 V or GND | 0 V to 5.5 V | +25 °C / Full | Typical ±0.1 µA / maximum ±5 µA | µA |
| Ioff | VI or VO = 5.5 V | 0 V | +25 °C / Full | Typical ±0.1 µA / maximum ±10 µA | µA |
| ICC | VI = 5.5 V or GND, IO = 0 | 1.65 V to 5.5 V | +25 °C / Full | Typical 0.1 µA / maximum 10 µA | µA |
| ΔICC | Input A at VCC - 0.6 V | 3 V to 5.5 V | Full | Maximum 500 µA | µA |
AC Switching and Test Conditions
The Rev A.1 PDF lists characterized propagation-delay values at +25 °C. These values are typical engineering references, not guaranteed production maxima; the specification states that they are ensured by design and characterization rather than tested in production.
| Parameter | VCC | Load condition | Temperature | Typical value | Unit |
|---|---|---|---|---|---|
| Propagation delay, tpd | 1.8 V ±0.15 V | CL = 30 pF, RL = 1 kΩ | +25 °C | 13.0 | ns |
| Propagation delay, tpd | 2.5 V ±0.2 V | CL = 30 pF, RL = 500 Ω | +25 °C | 5.1 | ns |
| Propagation delay, tpd | 3.3 V ±0.3 V | CL = 50 pF, RL = 500 Ω | +25 °C | 4.2 | ns |
| Propagation delay, tpd | 5.0 V ±0.5 V | CL = 50 pF, RL = 500 Ω | +25 °C | 3.3 | ns |
| Input capacitance, Ci | 3.3 V | VI = VCC or GND | +25 °C | 4 | pF |
| Power-dissipation capacitance, Cpd | 1.8 / 2.5 / 3.3 / 5.0 V | f = 10 MHz | +25 °C | 16 / 18 / 18 / 20 | pF |
Applicability note: Do not convert the listed typical values into guaranteed timing limits or a guaranteed maximum operating frequency. The PDF includes generic enable/disable waveform templates, but SN74LVC1G04 has no output-enable pin and does not provide tri-state operation.
Power Integrity, Input Handling and PCB Layout
The following layout is application guidance rather than a guaranteed reference circuit. Use the electrical tables for limits and validate the complete board power-distribution network and receiving logic interface.
- Place local bypassing close to the device: the application guidance shows a 0.1 µF capacitor; a parallel 1 µF capacitor may be used where the supply network requires additional local energy storage.
- Do not leave input A floating: the PDF requires an unused input to be held at VCC or GND.
- Apply the correct edge-rate limit: the maximum tr/tf entry changes from 20 ns/V at low supply to 5 ns/V at 5 V.
- Check receiving VIH: a 5.5 V-tolerant input does not guarantee that a low-VCC output can drive every higher-voltage receiver.
- Budget transition current: ΔICC is listed as 500 µA maximum under the stated VCC - 0.6 V input condition.
- Prevent output contention: Y is push-pull and has no output-enable control.
- Validate partial power-down: Ioff limits the device path; other PCB components can still create back-power paths.
SOT23-5 and SC70-5 Packages, Land Patterns and Packing
Both green package options share the same logical pin assignment but use different body dimensions, lead pitch, top marking and thermal impedance. Do not substitute one footprint for the other.
| Dimension | SOT23-5 | SC70-5 | Unit |
|---|---|---|---|
| Overall height A | 1.050 to 1.250 | 0.900 to 1.100 | mm |
| Body length D | 2.820 to 3.020 | 2.000 to 2.200 | mm |
| Body width E | 1.500 to 1.700 | 1.150 to 1.350 | mm |
| Overall lead span E1 | 2.650 to 2.950 | 2.150 to 2.450 | mm |
| Lead pitch e | 0.950 BSC | 0.650 BSC | mm |
| Outer lead pitch e1 | 1.800 to 2.000 | 1.300 BSC | mm |
| Lead width b | 0.300 to 0.500 | 0.150 to 0.350 | mm |
| Lead thickness c | 0.100 to 0.200 | 0.080 to 0.150 | mm |
| Lead length L | 0.300 to 0.600 | 0.260 to 0.460 | mm |
Application Guidance and Design Limitations
The Rev A.1 specification lists AC receivers, Blu-ray players and home theaters, desktop or notebook PCs, digital video cameras, mobile phones, personal navigation devices and portable media players. The inverter can restore signal polarity or isolate compact digital control paths after logic-level, edge-rate and load checks. These are possible use contexts, not end-product approvals.
AC ReceiversInvert local status, mute or control signals; the device does not process the analog audio path.
Blu-ray and Home TheaterRestore digital control polarity after confirming thresholds, propagation delay and fan-out.
Desktop and Notebook PCsUse for compact board-level status or enable inversion, not high-speed serial data switching.
Digital Video CamerasInvert digital control signals while respecting the stated input-transition and output-load limits.
Mobile PhonesEvaluate compact control-path inversion with full power-sequencing and standby-current validation.
Personal Navigation DevicesInvert local digital status or control lines; validate EMC and the complete navigation system.
Portable Media PlayersUse in low-static-power control logic after checking actual switching activity and load capacitance.SN74LVC1G04 Engineering FAQs
What logic function does SN74LVC1G04 implement?
It is one inverter. Y = ¬A, so a HIGH input produces a LOW output and a LOW input produces a HIGH output.
What supply range is recommended?
VCC is specified from 1.65 V to 5.5 V for operation. The PDF separately lists 1.5 V as the minimum data-retention supply; data retention does not establish normal logic operation.
Can the inputs accept 5.5 V when VCC is lower?
The recommended input range is 0 V to 5.5 V and input leakage is characterized across VCC = 0 V to 5.5 V. Still verify output-level compatibility and all board-level sequencing paths.
Is SN74LVC1G04 a Schmitt-trigger inverter?
No. The specification does not provide hysteresis thresholds. Use a Schmitt-trigger-qualified inverter when slow or noisy input transitions require hysteresis.
Does the output support tri-state or open-drain operation?
No. Y is a push-pull output with no enable pin. Do not connect it to another actively driven output or use it for wired logic.
What propagation-delay values are listed?
At +25 °C and the specified loads, typical tpd values are 13.0 ns at 1.8 V, 5.1 ns at 2.5 V, 4.2 ns at 3.3 V and 3.3 ns at 5 V. They are characterization values, not guaranteed maximum limits.
What does Ioff provide?
Ioff is specified with VCC = 0 V and VI or VO = 5.5 V, with ±10 µA maximum over the full temperature range. It limits the device path but does not eliminate other board-level back-power routes.
Which package should be selected?
SN74LVC1G04DBVR is SOT23-5 with C04F marking. SN74LVC1G04DCKR is SC70-5 with CCF marking. Both are MSL 3 and packed 3,000 units per reel.
Can input A be left open?
No. The PDF explicitly requires unused inputs to be held at VCC or GND. Pin 1 is N.C. and should not be used as a functional connection.
Do the listed applications establish product certification?
No. The application list identifies possible use contexts only. Qualification, safety, EMC, reliability and production validation remain system responsibilities.
This page summarizes the SN74LVC1G04 Rev A.1 product specification for component evaluation and engineering reference. It does not replace the complete controlled specification. Confirm the current revision, ordering code, marking, pin assignment, logic limits, absolute maximum ratings, DC and AC conditions, package tolerances, PCB layout, assembly process and qualification requirements before production release.
