CLRC66303HNY Replacement: NF663 Pin, Firmware, PCB and RF Review

What is CLRC66303HNY, and what does the HNY suffix mean?

CLRC66303HNY is the complete NXP ordering code for a CLRC663 plus multi-protocol NFC frontend in a wettable-flank HVQFN32 reel package. The suffix is important for procurement and qualification because a broad search for “CLRC663” can mix silicon revisions, package options, evaluation boards and third-party modules.

Can NF663 replace CLRC66303HNY?

Evaluate NF663 only if every selection gate below can be met.

CLRC66303HNY vs NF663: what is documented and what requires validation?

Published data show close functional and pin-assignment alignment between CLRC66303HNY and NF663, but the specified operating limits are not identical. The table separates manufacturer-documented characteristics from items that require verification on the target hardware.

Evidence basis: The comparison uses NXP CLRC663 data sheet Rev. 5.4 and the cited NF663 product documents. “Documented” means that a value appears in a manufacturer source; “validate” means that target-hardware testing is still required.

Are NF663 and CLRC66303HNY pin-compatible?

The published pin tables assign matching signal names to pins 1 through 32 and VSS to exposed pad 33. Use the grouped comparison for schematic review, then check each multifunction pin, I/O voltage and reset state against the controlled specifications.

Why consider NF663 as a CLRC66303HNY alternative?

NF663 may reduce PCB rework because its published package and pin assignments align with the primary CLRC66303HNY signal map while retaining the core functions of a host-controlled 13.56 MHz reader.

• PCB starting point: the published HVQFN32 package and terminal assignments allow engineers to review an existing design without first remapping every signal.
• Reader resources: multi-protocol operation, SPI, I²C, UART, FIFO, EEPROM, power management and balanced RF interfaces remain available for engineering evaluation.
• Evaluation path: the NF663 specification, product information and sample process support a staged document review, prototype build and qualification program.

Commercial boundary: request current pricing, minimum order quantity, lead time and documentation availability.

Review the NYFEA NF663 technical information and request samples for a migration build.

What does NF663 provide beyond package and pin alignment?

NF663 integrates the control, timing, memory and low-power resources expected in a host-controlled NFC/HF RFID reader frontend. These resources support systematic firmware porting after basic host communication has been established.

These current values are typical IC-level figures, not guaranteed end-product limits. Measure the complete assembly with its MCU, regulator, antenna network and final LPCD duty cycle.

Firmware and prototype migration from CLRC66303HNY to NF663

Do not assume that CLRC66303HNY register-level firmware will run unchanged on NF663. Compare reset defaults and interface startup first, then review register semantics, EEPROM and FIFO organization, commands, IRQ and timer behavior, protocol configuration, error recovery, LPCD and security integration.

1. Power and clock: verify every rail, reset state, interface strap and the 27.12 MHz clock.
2. Host communication: read a register with a known reset value, then confirm one write-and-readback transaction.
3. RF and protocol: confirm transmitter enable, field generation and one required card transaction before optimizing read range.
4. Application behavior: test anticollision, authentication, data access, error recovery and every production credential type.

For fault isolation, capture the first transceive command, IRQ0 and IRQ1 status, FIFO length and returned bytes. A successful UID read confirms card discovery only; it does not verify protected-data access, longer responses or write transactions. See the NF663 reader board bring-up guide for the detailed diagnostic sequence.

How should CLRC66303HNY SPI firmware be ported to NF663?

Port the NF663 transport and reset layer before reusing higher-level CLRC66303HNY command flows. First verify a register read with a known reset value, a write-and-readback operation, FIFO access, bounded IRQ handling and error recovery. Then add protocol loading and target-card transactions.

NF663 places the seven-bit register address in SPI address-byte bits 7:1 and uses bit 0 as the read/write flag: 1 for read and 0 for write. Start with SPI mode 0, MSB first, and an SPI bit rate no higher than the specified 10 Mbit/s limit. The optional C99 example keeps GPIO, SPI and timing behind four hardware-abstraction callbacks for MCU portability.

#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>

typedef struct {
    bool (*spi_write)(const uint8_t *data, size_t length);
    bool (*spi_exchange)(const uint8_t *tx, uint8_t *rx, size_t length);
    void (*nss)(bool high);          /* false = select NF663 */
    uint32_t (*millis)(void);
} nf663_t;

enum {
    NF663_REG_COMMAND      = 0x00,
    NF663_REG_FIFO_CONTROL = 0x02,
    NF663_REG_FIFO_LENGTH  = 0x04,
    NF663_REG_FIFO_DATA    = 0x05,
    NF663_REG_IRQ0         = 0x06,
    NF663_REG_IRQ1         = 0x07,
    NF663_REG_ERROR        = 0x0A,
    NF663_REG_VERSION      = 0x7F
};

enum {
    NF663_CMD_IDLE          = 0x00,
    NF663_CMD_TRANSCEIVE    = 0x07,
    NF663_CMD_LOAD_PROTOCOL = 0x0D,
    NF663_CMD_SOFT_RESET    = 0x1F
};

enum {
    NF663_FIFO_FLUSH = 0x10,
    NF663_IRQ0_IDLE  = 0x10,
    NF663_IRQ0_RX    = 0x04,
    NF663_IRQ0_ERR   = 0x02
};

typedef enum {
    NF663_OK = 0,
    NF663_E_IO,
    NF663_E_TIMEOUT,
    NF663_E_CHIP,
    NF663_E_BUFFER
} nf663_status_t;

static uint8_t nf663_spi_address(uint8_t reg, bool read)
{
    return (uint8_t)((reg << 1) | (read ? 1u : 0u));
}

static bool nf663_write_reg(nf663_t *dev, uint8_t reg, uint8_t value)
{
    const uint8_t frame[2] = { nf663_spi_address(reg, false), value };
    dev->nss(false);
    const bool ok = dev->spi_write(frame, sizeof frame);
    dev->nss(true);
    return ok;
}

static bool nf663_read_reg(nf663_t *dev, uint8_t reg, uint8_t *value)
{
    const uint8_t address = nf663_spi_address(reg, true);
    const uint8_t dummy = 0x00;
    dev->nss(false);
    bool ok = dev->spi_write(&address, 1);
    if (ok) ok = dev->spi_exchange(&dummy, value, 1);
    dev->nss(true);
    return ok;
}

static bool nf663_fifo_write(nf663_t *dev,
                             const uint8_t *data, size_t length)
{
    const uint8_t address = nf663_spi_address(NF663_REG_FIFO_DATA, false);
    dev->nss(false);
    bool ok = dev->spi_write(&address, 1);
    if (ok && length != 0u) ok = dev->spi_write(data, length);
    dev->nss(true);
    return ok;
}

static bool nf663_fifo_read(nf663_t *dev, uint8_t *data, size_t length)
{
    const uint8_t address = nf663_spi_address(NF663_REG_FIFO_DATA, true);
    const uint8_t dummy = 0x00;
    dev->nss(false);
    bool ok = dev->spi_write(&address, 1);
    for (size_t i = 0; ok && i < length; ++i)
        ok = dev->spi_exchange(&dummy, &data[i], 1);
    dev->nss(true);
    return ok;
}

static bool nf663_flush_fifo(nf663_t *dev)
{
    uint8_t control;
    return nf663_read_reg(dev, NF663_REG_FIFO_CONTROL, &control) &&
           nf663_write_reg(dev, NF663_REG_FIFO_CONTROL,
                           (uint8_t)(control | NF663_FIFO_FLUSH));
}

bool nf663_read_version(nf663_t *dev, uint8_t *version)
{
    return nf663_read_reg(dev, NF663_REG_VERSION, version);
}

bool nf663_soft_reset(nf663_t *dev)
{
    return nf663_write_reg(dev, NF663_REG_COMMAND,
                           NF663_CMD_SOFT_RESET);
}

bool nf663_load_protocol(nf663_t *dev,
                         uint8_t rx_protocol, uint8_t tx_protocol)
{
    const uint8_t parameters[2] = { rx_protocol, tx_protocol };
    return nf663_write_reg(dev, NF663_REG_COMMAND, NF663_CMD_IDLE) &&
           nf663_flush_fifo(dev) &&
           nf663_fifo_write(dev, parameters, sizeof parameters) &&
           nf663_write_reg(dev, NF663_REG_COMMAND,
                           NF663_CMD_LOAD_PROTOCOL);
}

nf663_status_t nf663_transceive(nf663_t *dev,
                                const uint8_t *tx, size_t tx_length,
                                uint8_t *rx, size_t *rx_length,
                                uint32_t timeout_ms,
                                uint8_t *chip_error)
{
    uint8_t irq0, error, fifo_control, fifo_length;

    if (!tx || !rx || !rx_length || tx_length > 512u)
        return NF663_E_BUFFER;

    if (!nf663_write_reg(dev, NF663_REG_COMMAND, NF663_CMD_IDLE) ||
        !nf663_flush_fifo(dev) ||
        !nf663_write_reg(dev, NF663_REG_IRQ0, 0x7F) ||
        !nf663_write_reg(dev, NF663_REG_IRQ1, 0x7F) ||
        !nf663_fifo_write(dev, tx, tx_length) ||
        !nf663_write_reg(dev, NF663_REG_COMMAND, NF663_CMD_TRANSCEIVE))
        return NF663_E_IO;

    const uint32_t start = dev->millis();
    for (;;) {
        if (!nf663_read_reg(dev, NF663_REG_IRQ0, &irq0))
            return NF663_E_IO;
        if ((irq0 & NF663_IRQ0_ERR) != 0u) break;
        if ((irq0 & (NF663_IRQ0_RX | NF663_IRQ0_IDLE)) != 0u) break;
        if ((uint32_t)(dev->millis() - start) >= timeout_ms) {
            (void)nf663_write_reg(dev, NF663_REG_COMMAND, NF663_CMD_IDLE);
            return NF663_E_TIMEOUT;
        }
    }

    if (!nf663_read_reg(dev, NF663_REG_ERROR, &error))
        return NF663_E_IO;
    if (chip_error) *chip_error = error;
    if (error != 0u) return NF663_E_CHIP;

    if (!nf663_read_reg(dev, NF663_REG_FIFO_CONTROL, &fifo_control) ||
        !nf663_read_reg(dev, NF663_REG_FIFO_LENGTH, &fifo_length))
        return NF663_E_IO;

    const size_t available =
        ((size_t)(fifo_control & 0x03u) << 8) | fifo_length;
    if (available > *rx_length) {
        *rx_length = available;
        return NF663_E_BUFFER;
    }

    *rx_length = available;
    if (available != 0u && !nf663_fifo_read(dev, rx, available))
        return NF663_E_IO;

    return NF663_OK;
}

NF663 PCB reference design: what it can and cannot establish

Treat the assembled-board and zoning images below as layout and bring-up references. They show how to separate the host interface, reader IC, clock, power, balanced transmitter network and antenna for measurement; they do not establish a production-qualified implementation.

Power domainsKeep VDD, PVDD and TVDD within the specified 3.0 V to 5.5 V range. Place local decoupling at the relevant pins, then measure startup behavior, ripple and transmitter-current headroom on the assembled board.

ClockPlace the 27.12 MHz crystal and its load network close to XTAL1 and XTAL2. The published reference specifies 10 pF load capacitance, ±250 ppm frequency tolerance and ESR up to 100 Ω; verify the selected crystal and PCB parasitics.

Host interfaceRoute SPI over a continuous return path and provide accessible test points for NSS, SCK, MOSI, MISO, IRQ and reset. Begin with SPI mode 0, MSB first, and remain within the 10 Mbit/s limit.

RF pathRoute TX1 and TX2 symmetrically through the EMC filter and matching network. Treat RXP, RXN and VMID as sensitive analog nodes, separated from clocks, switching-regulator nodes and fast digital edges.

Antenna interfaceDefine the impedance-measurement plane at the antenna connector or matching network. Do not copy CLRC66303HNY component values without measuring the antenna and retuning the complete RF path.

Release evidenceArchive the board revision, stack-up, schematic, matching-network BOM, antenna impedance, current waveforms, card matrix, firmware commit, temperature and enclosure state.

Bring-up should progress from rail and clock verification to register access, IRQ and FIFO behavior, RF field generation, and the complete required-card matrix.

Can the CLRC66303HNY antenna and LPCD settings be reused with NF663?

Do not release an NF663 design using unverified CLRC66303HNY RF component values or LPCD thresholds. The antenna geometry may be retained as a controlled starting point, but the filter, matching network, receiver path and low-power detection behavior must be characterized again.

Normal communication range and LPCD wake range require separate acceptance criteria. Measure antenna impedance at a documented calibration plane, transmitter current and waveform, receiver margin, card-transaction success, LPCD I/Q baseline, false-wake rate, missed-card rate and wake-to-transaction time. Repeat the tests with the final enclosure, battery, display, cables, ferrite, nearby metal and required cards.

For the detailed method, use the CLRC663 antenna and read-range guide and the CLRC663 LPCD I/Q register debugging guide.

How should an NF663 migration be qualified for release?

The release workflow should convert every compatibility claim into a requirement, test method, result and responsible owner. A feature comparison can screen a candidate; design approval requires documented qualification.

Make each test reproducible: record the board serial number and revision, firmware commit, antenna and matching-network BOM, card model, supply voltage, temperature, orientation, distance, trial count, failures and recovery behavior. Define pass criteria before testing. For LPCD, report false wakes per observation period and missed detections per presentation count together with current consumption and wake latency.

Preserve raw logs and failed cases. A documented failure is more useful than an isolated “works” result because it defines a repeatable boundary condition and a measurable target for the next revision.

Primary technical sources

• NXP CLRC663 data sheet, Rev. 5.4 — specifications, limits, package and ordering.
• NXP CLRC663 plus product page — lifecycle and development resources.
• NXP AN12657 — host-interface commands and protocol examples.
• NXP AN11019 — antenna matching and measurement.
• NXP AN11145 — LPCD design and tuning.
• NYFEA NF663 product page and product specification — NF663 specifications, pins, registers and RF guidance.

Engineering basis: Use revision-controlled manufacturer specifications for design decisions and qualify NF663 on the target hardware before release.

Disclosure: NYFEA supplies NF663.