CLRC66303HNY Hardware Design: From SPI Bring-Up to NFC Command Writes

Start here: get a stable CLRC66303HNY register response

SPI selection occurs after cold reset, power-up or hard-power-down exit. Strap IFSEL0 to VSS and IFSEL1 to PVDD, keeping both stable through interface detection.

NXP’s COTI, CITO and NTS correspond to MOSI, MISO and active-low NSS/CS in this guide.

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Use SPI Mode 0, MSB first

Set CPOL = 0 and CPHA = 0: SCK idles low; data is sampled on rising edges. Begin around 100 kHz. The datasheet maximum is 10 Mbit/s, subject to board timing and signal integrity.

Read VersionReg before attempting card detection

Read VersionReg at 0x7F using (address << 1) | 1 plus a dummy byte. Transmit 0xFF, 0x00; discard the first MISO byte and read the value from the second.

Keep NSS low across both bytes and high for at least 50 ns between commands. Disable MCU NSS pulses that would split the transaction.

SPI returns 0x00 / 0xFF: follow the captured signal

Capture NSS, SCK, MOSI and MISO at the reader pins during one version read. Choose the first failed check below; a constant byte alone does not identify a damaged IC.

1. No SCK at the reader? Check that the MCU transfer starts, the pin multiplexer selects SPI and the SCK connection reaches pin 29. Retest until the requested frame appears at the IC.
2. NSS rises between bytes, or MOSI is not FF 00? Correct the mode, bit order and address framing; use continuous software-controlled NSS across the transfer. Compare the next capture with the timing figure.
3. The frame is correct, but MISO stays fixed? Check power at the IC, PDOWN and IFSEL levels at startup, then MISO continuity and competing drivers. Repeat the same read after each correction.
4. The trace contains 1A, but firmware reports another value? Inspect the second receive byte and buffer handling. If failures appear only with RF active, capture the supply disturbance before changing SPI settings.

Ready to continue: repeated reads return 0x1A across fresh power-ups. Save the trace and observed byte; then proceed to RF diagnosis.

Source: NXP CLRC663 Rev. 5.4, §8.4.2, Tables 16 and 20, and §9.25 Version register.

Core C code for CLRC663 SPI register access

Use the supplied C99 driver for single-register reads and writes. After adapting the board_hal_* functions and completing startup, call the version check:

uint8_t observed = 0;
int status = clrc66303_check_version(&observed);
/* status ==  0: observed is 0x1A (CLRC66303)
 * status == -1: SPI transfer failed
 * status == -2: read succeeded; inspect the other version byte
 */

/* CLRC66303 SPI register access example, C99.
 * Adapt every board_hal_* function to the target MCU.
 * Configure SPI mode 0, MSB first, initially 100 kHz (bring-up choice).
 * This is a transport example, not a complete NFC protocol driver.
 */
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>

/* Blocking transfer; return only after the last SCK edge.
 * Return false on timeout/error. Do not toggle NSS inside this function.
 */
extern bool board_hal_spi_transfer(const uint8_t *tx, uint8_t *rx,
                                   size_t length);
extern void board_hal_nss(bool high);
/* Meet the datasheet NSS-high interval: at least 50 ns.
 * Account for GPIO, timer and compiler behavior on the actual MCU.
 */
extern void board_hal_nss_high_gap(void);

#define CLRC663_VERSION_REG       UINT8_C(0x7F)
#define CLRC66303_EXPECTED_VERSION UINT8_C(0x1A)

/* Serialize access to this SPI bus for the whole transaction. */
static bool clrc663_frame(const uint8_t tx[2], uint8_t rx[2])
{
    board_hal_nss(false);
    const bool ok = board_hal_spi_transfer(tx, rx, 2u);
    board_hal_nss(true);       /* Release NSS even after a bus error. */
    board_hal_nss_high_gap();
    return ok;
}

bool clrc663_read_reg(uint8_t reg, uint8_t *value)
{
    if (reg > UINT8_C(0x7F) || value == NULL) {
        return false;
    }
    const uint8_t tx[2] = {
        (uint8_t)((reg << 1u) | 1u),  /* LSB = 1: read. */
        UINT8_C(0x00)                /* Dummy byte generates clocks. */
    };
    uint8_t rx[2] = {0u, 0u};
    if (!clrc663_frame(tx, rx)) {
        return false;
    }
    *value = rx[1];             /* Address-phase MISO is not the value. */
    return true;
}

bool clrc663_write_reg(uint8_t reg, uint8_t value)
{
    if (reg > UINT8_C(0x7F)) {
        return false;
    }
    const uint8_t tx[2] = {
        (uint8_t)(reg << 1u),   /* LSB = 0: write. */
        value
    };
    uint8_t rx[2] = {0u, 0u};
    return clrc663_frame(tx, rx);
}

/* Call after valid rails, settled IFSEL straps and PDOWN release.
 *  0 = expected CLRC66303 version; -1 = bus error; -2 = other version.
 * Log the observed byte; VersionReg is not an authenticity test.
 */
int clrc66303_check_version(uint8_t *observed)
{
    uint8_t version = 0u;
    if (!clrc663_read_reg(CLRC663_VERSION_REG, &version)) {
        return -1;
    }
    if (observed != NULL) {
        *observed = version;
    }
    return version == CLRC66303_EXPECTED_VERSION ? 0 : -2;
}

Download the core C source (TXT) · The package also includes a host-side framing test.

Adapt the blocking HAL functions, preserve the full NSS frame and serialize shared-bus access. Use the signal checks above to separate a framing error from a board fault. This driver does not implement card polling, FIFO/IRQ handling or anticollision.

Reference: NXP AN12657, operation without a library. The example passed host-side syntax/framing checks; hardware validation remains required.

Registers respond, but there is no RF field: isolate the failing stage

Log the board revision, firmware, supply, antenna and card. Change one variable at a time and resolve the first failing stage in the sequence below.

Download the bring-up record to log expected results, observations and next actions.

Prerequisites: valid rails, defined reset/interface selection, a running clock and stable register reads. Keep the board, firmware, card and antenna configuration fixed while comparing measurements.

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Find where the RF path stops

Request field activation with the intended protocol configuration. Capture TVDD during the attempt and check RF activity using an appropriate differential or near-field fixture. Never connect a grounded probe across TX1/TX2.

1. TVDD falls or register communication becomes unstable: resolve supply capacity, local decoupling and ground-return issues first. Repeat field activation and confirm the rail stays within its operating limits.
2. TVDD is stable, but no TX activity is observed: inspect oscillator operation, transmitter-enable configuration and command/error status. Confirm host writes reached the intended registers before editing the antenna network.
3. TX activity exists, but the antenna has little field: follow the filter-to-antenna path. Check population, solder joints and coil continuity with power off; assess matching under controlled conditions. Compare signals before and after the affected stage.
4. The antenna has a field, but the card stays silent: move to protocol and receiver checks below. Field presence alone does not verify modulation, receive sensitivity or a valid polling sequence.

Retest: field activation is repeatable without supply collapse; a known supported card completes the intended exchange at a fixed position. Record attempts, successful exchanges and errors before testing range.

Field present? Use the next symptom

References: NXP AN12657 for command-level operation; AN11019 for the RF network. Related: CLRC663 register and LPCD troubleshooting.

What is CLRC66303HNY, and what does HNY mean?

CLRC66303HNY is an ordering variant of NXP’s CLRC66303 NFC frontend. It handles RF and reader functions for ISO/IEC 14443 A/B, ISO/IEC 15693 and other documented modes; the host runs protocol and application software.

Keep the complete ordering code on the BOM. Check package, packing label and lot traceability at incoming inspection; a similar top mark cannot identify the reel variant.

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Sources: NXP CLRC663 plus product overview; CLRC663 Rev. 5.4, ordering information and §15 package marking.

CLRC66303HNY pinout: HVQFN32 pin groups and pad 33

The package has 32 perimeter terminals and exposed center pad 33. Connect pad 33 to VSS. Include it in both the schematic symbol and PCB footprint.

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SCL/SDA pins 23/24 belong to the separate SAM interface. Auxiliary/test functions use pins 1–6, 10 and 11; consult the pin map and NXP’s unused-pin guidance before assigning pull resistors.

Source: NXP CLRC663 Rev. 5.4, §7 and Table 4. The HVQFN32 mapping must not be applied to the VFBGA36 variant.

How to connect VDD, PVDD, TVDD, AVDD and DVDD

VDD, PVDD and TVDD are external inputs that may share a suitable source. AVDD and DVDD are internal regulator buffer nodes requiring the capacitors shown below.

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Measure VDD and PVDD together during startup. At field activation, capture TVDD minimum voltage, ripple and current step at pin 18 with a short probe return.

The HVQFN32 ambient range is −40 to +105 °C under specified PCB and exposed-pad conditions. Check junction temperature, transmitter dissipation and the assembled thermal path.

Source: NXP CLRC663 Rev. 5.4, §8.9.1, Table 251 and the regulator characteristics. Measurement sequence is engineering guidance, not a reported board test.

27.12 MHz crystal selection, layout and safe probing

Connect the 27.12 MHz crystal to XTAL1/XTAL2, pins 19/20. The RF carrier is 13.56 MHz; a crystal at that lower frequency is unsuitable.

NXP specifies 10 pF typical crystal load, 100 Ω maximum ESR and 100 µW maximum drive. Also check frequency tolerance and oscillator operating conditions.

PDOWN high stops the oscillator. Check that it is low and startup timing has elapsed. For intermittent oscillation, inspect supply ramp, loading, contamination and crystal placement.

Sources: NXP CLRC663 Rev. 5.4, Table 44 and power-down behavior; NXP AN14518, Crystal Oscillator Design Guide. Layout and probing recommendations require verification on the target board.

CLRC663 application circuit, explained block by block

The NXP circuit connects the host interface, supplies, oscillator, transmit network and receiver bias. Its architecture is a reference; antenna matching values remain board-specific.

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1. MCU, IRQ and PDOWNUse the verified host wiring; make command status observable.
2. Three external supply inputsCheck the supply map at the IC during field activation.
3. 27.12 MHz oscillatorComplete the startup and probing checks before interpreting timeouts.
4. Differential transmitterTX1/TX2 feed the RF network; TVSS returns transmitter current.
5. EMC low-pass filterL0/C0 suppress harmonics and interact with downstream impedance. Inspect population and routing.
6. Antenna matching and dampingSelect matching and damping for the actual coil, enclosure and card population.
7. Receiver and VMID referenceCheck receive coupling, scaling and bias separately from field strength.

What read range should you specify for CLRC66303HNY?

Read distance depends on antenna impedance, matching, card type, orientation, supply and enclosure. Measure the assembled RF network before choosing matching and damping values.

• Define the operating region: specify the allowed card distance, lateral offset and angle relative to the finished enclosure.
• Measure successful exchanges: record completed transactions out of attempted transactions, with a latency limit and a defined retry policy.
• Repeat at the design limits: use the required card types, supply and temperature conditions, including nearby metal. Record RF settings and component values with the results.

How do TX1/TX2, RXP/RXN and VMID help locate a fault?

Sources: NXP CLRC663, Figure 36 and §14; NXP AN11019 antenna design guide. Related design discussion: CLRC663 antenna design and read-range checks.

Real PCB example: NXP CLEV6630B evaluation board

The real NXP CLEV6630B board pairs CLRC66303 with an LPC1769 over SPI. Its photo shows the reader, power, clock and antenna layout; the reel suffix is unspecified.

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1. Power selection

   Upper-edge jumpers select the reader rails. Follow the board-specific jumper diagram before applying power.

2. Host / interface selection

   Inspect the interface straps and host-disconnect paths. An external MCU must not fight the on-board LPC1769.

3. Reader crystal region

   XT300 is the 27.12 MHz reader crystal in the schematic. XT200 is the separate 12 MHz MCU crystal.

4. RF network

   The filter, matching and receiver components sit between the reader and antenna connection.

5. Antenna area

   The supplied antenna is 65 × 65 mm. Its geometry and nearby metal are part of the reference configuration.

Photo: NXP AN11022 Rev. 1.7, Figure 1, © NXP B.V. Numbered overlays identify approximate regions; the original photograph is unchanged.

Before fabrication: make the failing signals accessible

Check the footprint against the pin map. Provide test access to the supply rails, NSS, SCK, IRQ and PDOWN so the diagnostic sequence can be repeated without disturbing the RF or crystal layout.

Reference-board details: NXP AN11022, §2, Figures 1, 8 and 9.